Agilex™ 7 FPGA – Hello World on the Nios® V/m Processor Design Example

Agilex™ 7 FPGA – Hello World on the Nios® V/m Processor Design Example

787040
3/5/2024

Introduction

Nios® V/m processor-based Hello World design example on the Agilex™ 7 FPGA.

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

Intel Agilex® 7 FPGA F-Series 014 (R24B) AGFB014R24B2E2V

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

24.1

Other Tags

Validated in Quartus and Board

IP Cores (3)
IP Core IP Core Category
Nios V/m Processor Intel FPGA IP Processor
Configuration Clock Intel FPGA IP Other
In-System Sources & Probes Intel FPGA IP Other

Detailed Description

Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series

Intel Agilex® 7 FPGA F-Series 014 (R24B) AGFB014R24B2E2V

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

24.1

Other Tags

Validated in Quartus and Board