Introduction
Development Kit
Intel Agilex® 7 FPGA F-Series Development Kit DK-DEV-AGF014E3ES
| IP Core | IP Core Category |
|---|---|
| On-Chip Memory (RAM or ROM) | OnChipMemory |
| Reset Controller | QsysInterconnect |
| MM Interconnect | QsysInterconnect |
| Memory-Mapped Multiplexer | QsysInterconnect |
| Memory-Mapped Router | QsysInterconnect |
| Avalon-MM Slave Agent | QsysInterconnect |
| Avalon-MM Master Translator | QsysInterconnect |
| Memory-Mapped Demultiplexer | QsysInterconnect |
| Memory-Mapped Burst Adapter | QsysInterconnect |
| Avalon-ST Single Clock FIFO | QsysInterconnect |
| Avalon-MM Slave Translator | QsysInterconnect |
| Avalon-MM Master Agent | QsysInterconnec |
Detailed Description
Configuration via Protocol (CvP) is a configuration scheme supported in Intel® Agilex™ device families. The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the Intel® FPGA fabric through the PCI Express* ( PCIe* ) link, and is available for Endpoint variants only. This document describes the CvP configuration scheme for Intel® Agilex™ device family.
Starting version 23.1, this design example leverages the board aware flow in Platform Designer. Additional information can be found in the Using the Board-Aware Flow in Platform Designer section of the Intel® Quartus® Prime Pro Edition User Guide: Platform Designer document.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>
Development Kit
Intel Agilex® 7 FPGA F-Series Development Kit DK-DEV-AGF014E3ES