Introduction
This design example shows the chip ID reading functionality using the Avalon® Streaming Interface Intel® FPGA IP with an Intel Agilex® 7 FPGA Development Kit. The chip ID reading functionality is implemented in Verilog and connects with the IP communicating with flash memory.
IP Cores
(3)
| IP Core | IP Core Category |
|---|---|
| Mailbox Client with Avalon Streaming Interface Intel FPGA IP | Other |
| Reset Release Intel FPGA IP | Other |
| In-System Sources & Probes Intel FPGA IP | Other |
Detailed Description
In Intel Agilex 7 FPGAs IP to perform chip ID reading is no longer available. Thus, custom logic has to be created and connected to Mailbox Avalon® ST Client Intel FPGA IP to perform chip ID reading. This reference design indicates the usage of Mailbox Avalon® ST Client Intel FPGA IP to perform chip id reading. The tutorial is demonstrated using Signal Tap.