Introduction
| IP Core | IP Core Category |
|---|---|
| JTAG-Over-Protocol Intel FPGA IP | Debug and Performance |
| IOPLL Intel FPGA IP | ClocksPLLs and Resets |
| Reset Release Intel FPGA IP | Configuration and Programming |
| Intel L-/H-Tile Avalon memory mapped for PCI Express | PCI Express |
Detailed Description
The JTAG-Over-Protocol Intel® FPGA IP gives you access to JTAG debugging on the FPGA device without a physical connection to the JTAG pins on the device. The IP requires additional infrastructure to communicate with the JTAG server. Because system designs often differ, you must create this additional infrastructure to account for your system design.
This design example uses the following components to create simple custom communication infrastructure:
• Open source etherlink application
• Open source Linux universal I/O PCIe drivers (uio_pci_driver)
• L-tile Avalon® Memory-Mapped Intel FPGA IP for PCI Express*
The debugging applications (like Signal Tap ) is run on the host machine and communicate with the JTAG server on the same machine. The etherlink application listens to the JTAG server and converts TCP/IP data into PCIe MMIO transactions that are sent to the FPGA device where the PCIe MMIO transactions are forwarded to the JTAG-Over-Protocol (JOP) Intel FPGA IP over an Avalon Memory-Mapped interface. The JOP IP translates the communication it receives from the JTAG server into JTAG signals for the FPGA debug logic. Debug data is sent back to the JTAG server and debug application in the reverse of this flow.
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>
Note:
* ACDS Version: 22.1 Pro