Introduction
| IP Core | IP Core Category |
|---|---|
| Altera In-System Sources & Probes | SimulationDebugVerification |
| Reset Controller | QsysInterconnect |
| MM Interconnect | QsysInterconnect |
| Avalon-MM Master Translator | QsysInterconnect |
| Avalon-MM Slave Translator | QsysInterconnect |
| altera_config_stream_endpoint | Debug & Performance |
| altera_jtag_avalon_master | QsysInterconnect |
| Avalon Packets to Transaction Converter | QsysInterconnect |
| Avalon-ST Single Clock FIFO | QsysInterconnect |
| Avalon-ST Channel Adapter | QsysInterconnect |
| Avalon-ST Bytes to Packets Converter | QsysInterconnect |
| Avalon-ST JTAG Interface | QsysInterconnect |
| Avalon-ST Packets to Bytes Converter | QsysInterconnect |
| Avalon-ST Timing Adapter | QsysInterconnect |
| Top level generated instrumentation fabric | Debug & Performance |
| Altera SDM Mbox Bridge | Configuration and Programming |
| Altera SDM GPO | Configuration and Programming |
| Altera SDM GPI | Configuration and Programming |
| Altera FPGA2SDM Bridge | Configuration and Programming |
| Altera SDM IRQ | Configuration and Programming |
| Altera SDM2FPGA Bridge | Configuration and Programming |
| Avalon-ST Handshake Clock Crosser | QsysInterconnect |
| Memory-Mapped Multiplexer | QsysInterconnect |
Detailed Description
The Mailbox Client Intel FPGA IP is a bridge between a host and the Secure Device Manager (SDM). The Mailbox Client Intel FPGA IP is used to send commands to the SDM and return responses to the host. The Mailbox Client Intel FPGA IP is an Avalon MM slave component that must connect to an Avalon MM Master.
In this reference design, a JTAG-to-Avalon Master Bridge IP acts as the host controller connecting to the Mailbox Client Intel FPGA IP core. The JTAG-to-Avalon Master Bridge IP translates the commands it receives from System Console to Avalon Memory-Mapped (Avalon MM) format that the Mailbox Client Intel FPGA IP requires. The Mailbox Client Intel FPGA IP then drives commands and receives responses from the SDM.
The rsu1.tcl script provides examples to perform the available command functions supported by the SDM. You can run the functions available in the rsu1.tcl script vie System Console of the Intel Quartus Prime Pro software to perform the following operations,
- Read FPGA IDCODE
- Read FPGA CHIP ID
- QSPI flash access operations such as reading and writing to flash memory
- Remote System Update (RSU) operations such as reading RSU status, triggering reconfiguration to another image in flash, and updating a configuration image in flash.
The rsu1.tcl script can be downloaded from the link provided below.
For more details
1. Refer to the Mailbox Client Intel FPGA IP User Guide
2. Refer to Chapter 4. Remote System Update (RSU) in the Intel Agilex Configuration User Guide