Intel Agilex® 7 FPGA – AN911: Achieving Timing Closure When Using Top I/O Sub Bank Design Example

Intel Agilex® 7 FPGA – AN911: Achieving Timing Closure When Using Top I/O Sub Bank Design Example

714634
12/13/2022
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Introduction

This application note describes two methods to resolve these timing violations using the GPIO Intel® FPGA IP core. The analysis in this document focuses on the input datapaths from the GPIO Intel FPGA IP core to the FPGA core. There are 3 project revisions for this application note: - top - original design example with setup timing violation. - top_w1 - design example using a negative edge clock latching solution. - top_w2 - design example using a half-rate transfer mode solution.

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

22.3
IP Cores (2)
IP Core IP Core Category
Altera GPIO Other
Altera IOPLL ClocksPLLsResets

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 22.3.0 Pro

Design Details

Device Family

Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

22.3