ADV2409 Stratix® 10: Amendment of Global Reference Clock Promotion Feature Support for LVDS SERDES RX in non-DPA Mode

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Intel® FPGA PCNs, PDNs, and ADVs Index Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support

827336
2024-07-18
Public

Description

Altera is notifying customers of important updates to the LVDS SERDES global reference clock promotion support coverage.

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