Introduction to SDC-on-RTL and Early Timing Analysis

Description

Timing analysis plays a pivotal role in the FPGA design cycle, and precise constraints are essential for meeting timing requirements. The Quartus® Prime Pro software offers the SDC-on-RTL feature, enabling you to apply constraints directly to the hierarchical pins within your RTL design. In this video, we'll explore the fundamentals of SDC-on-RTL and delve into the advantages it brings to your new design projects.