AN 351: Simulating Nios® II Processor Designs

Download

Nios® II Processors FPGA Documentation Index Nios® II Processors Support Altera® FPGA IP Resource and Documentation Collection Altera® FPGA IP Resource and Documentation Collection

654443
2013-11-02
Public

Description

This application note describes the process of generating an RTL simulation environment using Nios® II example designs, Qsys ,and the Nios II IDE.

Usage instructions