653862
2012-09-30
Public
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Description
Describes the hierarchical clock networks and phase locked loops (PLLs). Reconfigure the PLL counter clock frequency and phase shift in real time and dynamically adjust the output clock phase shift.
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Cyclone® IV Device Handbook, Volume 1, Chapter 9: SEU Mitigation
Describes the cyclical redundancy check (CRC) error detection feature in user mode and how to recover from soft errors.
Cyclone® IV Device Handbook, Volume 1, Chapter 2: Logic Elements and Logic Array Blocks
This chapter provides features and details on how LEs work, how LABs contain groups of LEs, and how LABs interface with the other blocks in Cyclone® IV devices.
Cyclone® IV Device Handbook, Volume 2, Chapter 3: Dynamic Reconfiguration
Describes and provides examples about the different modes to dynamically reconfigure different portions of the transceivers without powering down any part of the device.
Cyclone® IV Device Handbook, Volume 1, Chapter 7: External Memory Interfaces
Describes the memory interface pin support and the external memory interface. Cyclone® IV devices can easily interface with a broad range of external memory devices, including DDR2 SDRAM, DDR SDRAM, and QDR II SRAM.
Cyclone® IV Device Handbook, Volume 1, Chapter 8: Configuration and Remote System Upgrades
Describes the configuration and remote system upgrades using volatile SRAM cells to store configuration data.
Cyclone® IV Device Handbook, Volume 3: Device Datasheet
Cyclone® IV Device Handbook, Volume 3: Device Datasheet
Cyclone® IV Device Handbook, Volume 2: Transceivers
Cyclone® IV Device Handbook, Volume 2: Transceivers
Cyclone® IV Device Handbook, Volume 1, Chapter 11: Power Requirements
Describes information about external power supply requirements, hot socketing specifications, power-on reset (POR) requirements, and their implementation in Cyclone® IV devices.
Cyclone® IV Device Handbook, Volume 1, Chapter 10: JTAG Boundary-Scan Testing
Describes the boundary-scan test (BST) features that support IEEE Std. 1149.1 and IEEE Std. 1149.6. The IEEE Std. 1149.6 (AC JTAG) is only supported on the high-speed serial interface (HSSI) transceivers in Cyclone® IV GX devices.
Cyclone® IV Device Handbook, Volume 1, Chapter 1: FPGA Device Family Overview
Built on an optimized low-power process, the Cyclone® IV device family offers lowest power, high functionality with the lowest cost with 3.125 Gbps transceivers
Cyclone® IV Device Handbook, Volume 3, Chapter 1: Device Datasheet
Describes the electrical and switching characteristics including operating conditions, power consumption, transceiver specifications, transceiver core, and periphery performance.
Cyclone® IV Device Handbook, Volume 1, Chapter 3: Memory Blocks
Embedded memory structure consists of columns of M9K memory blocks configured to provide various memory functions, such as RAM, shift registers, ROM, and FIFO buffers.
Cyclone® IV Device Handbook, Volume 1, Chapter 4: Embedded Multipliers
A combination of on chip resources and external interfaces that help increase performance, reduce system cost, and lower the power consumption of digital signal processing (DSP) systems.
Cyclone® IV Device Handbook, Volume 1, Chapter 6: I/O Features
Describes the I/O and high speed I/O capabilities driven by the diversification of I/O standards in many low cost applications, and the significant increase in required I/O performance.
Cyclone® IV Device Handbook, Volume 1: Device Core, I/O Interfaces, and System Integration
Cyclone® IV Device Handbook, Volume 1: Device Core, I/O Interfaces, and System Integration
Cyclone® IV Device Handbook, Volume 2, Chapter 1: Transceivers Architecture
This chapter discusses Cyclone® IV GX transceivers and supported protocols.
Cyclone® IV Device Handbook, Volume 2, Chapter 2: Reset Control and Power Down
Multiple reset signals control the transceiver channels independently. Individual reset signals for each channel instantiated and one power-down signal for each transceiver block.