Implementing the Unified FFT Intel® FPGA IP

Description

This video will show the users how to implement the variable size FFT operation with the Unified FFT Intel® FPGA IP with 16 bits input and output width. The purpose of this video is to assist users to have quick start with the latest Unified FFT Intel FPGA IP in Intel Stratix® 10 FPGA. This video will also demonstrate to the user on how to perform functional simulation with FFT operation with 16 bits input and output using the pruning feature. This video will cover IP configuration, Modelsim* simulation and result analysis for better illustration and to facilitate users' understanding