HEV/EV System

FPGA Use Case Example

Differentiation While Lowering Costs

• Reducing the size and weight of individual components in automotive system design is critical because it directly affects vehicle fuel efficiency and cost.
• Intel FPGAs enable faster switching frequencies (50 kHz) in DC/DC conversion applications, resulting in smaller, lighter, more efficient motors and external components. By migrating designs from traditional MCUs to FPGAs, it is possible to achieve a 5X improvement in switching frequencies and a 5X reduction in size in passive components (inductors and capacitors).
• In electric motor control, faster switching frequencies enable motor control loop update times in microseconds, which are required to meet the industry’s need to reduce system costs and weight by using smaller, faster spinning motors.

Motor Inverter and DC/DC Converter System

Design Flows for Everyone

For Hardware Engineers:

Our Intel® Quartus® Prime design software is the programmable logic industry’s number-one software in performance and productivity for FPGA and CPLD design. Using the tool, you can accelerate your designs to achieve faster compile times, automatically generate interconnect logic with Platform Designer, and optimize power consumption with the Power Analyzer. Our free, no-license-required Intel® Quartus® Prime Lite Edition Software supports designs for automotive-grade FPGAs and CPLDs.

Intel and its IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimized for our devices.

For Algorithm Engineers:

We offer a model-based design flow that simplifies your design effort, eliminating the need to develop your algorithm in VHDL or Verilog HDL. Our DSP Builder for Intel FPGAs development tool shortens your algorithm design cycle, enabling you to design your DSP algorithm in MathWorks* MATLAB*/Simulink* environment. It generates register transfer level (RTL) code to integrate into our design environment easily. You can model and simulate your system, implement complex algorithms in hardware, partition the hardware/software elements, and fine-tune the performance to the exact needs of your application.

For Software Engineers:

Once you have selected a suitable processor for your embedded system, you can jump start your software development with our Intel SoC FPGA Embedded Development Suite (SoC EDS).

The SoC EDS is a comprehensive tool suite for embedded software development on Intel SoCs. It contains development tools, utility programs, run-time software and application examples to expedite firmware and application software of SoC embedded systems.

The Nios® II Embedded Design Suite (EDS) is a comprehensive development package for Nios II software design. The Nios II EDS contains not just development tools, but also software, device drivers, bare metal Hardware Abstraction Layer (HAL) library, a commercial-grade network stack software and an evaluation version of a real-time operating system.

Motor Control Designs with an Integrated FPGA Design Flow

This white paper describes a recommended design flow that leverages Intel® FPGAs’ adaptability, variable-precision digital signal processing (DSP), and integrated system-level design tools for motor control designs. Motor-driven equipment designers can take advantage of the performance, integration, and efficiency benefits of this design flow.

Download white paper ›

Motor Inverter Solution

Today, microcontroller units (MCUs) control most power electronics, mainly because MCUs are low cost and provide a high level of integration. MCUs are typically programmed in C or Assembly language and are well-suited to algorithms that are executed sequentially at a rate within the MCU’s capability. Designers of traditional MCU-based systems are facing new challenges, however, as their applications demand faster sampling rates and more complex algorithms.

FPGAs are gaining acceptance in high-performance power electronics control systems due to their speed, flexibility, and integrated design tools. These devices are well suited for electric vehicles (EV) drive system applications such as Valuable Voltage DC/DC converters (VVC) and motor control due to their parallel architecture and ability to handle multiple complex algorithms simultaneously in hardware.

FPGAs offer:

• Increased processing speed: Algorithms can be accelerated and parallelized in an FPGA’s programmable hardware.
• Flexible design of interfaces: For example, parallel analog-to-digital converter (ADC) interfaces and pulse-width modulation (PWM) outputs can be added to support new inverter topologies.
• Ease of programming: Main control loop code can be maintained in C and run on hard or soft processors. Code for hardware acceleration can be fixed or floating point and written in C or MATLAB/Simulink.
• Ease of integration: Interfaces for encoders or resolvers, sigma-delta ADCs, and external communications can be built into the FPGA fabric.
• Cost effectiveness: Part count can be reduced, development streamlined, and the platform can be updated without affecting the PCB.

IPM Motor Control with FPGA by Model-Based Design

Intel has developed a reference design of an Interior Permanent Magnet (IPM) motor control with Direct Torque and Flux Control using a Space Vector Modulation (DTFC-SVM) algorithm in a Model-Based Design (MBD). The simulation result shows notable torque ripple reduction compared to a Field-Oriented Control (FOC) algorithm. It also shows a significant advantage over MCU-based, DTFC-SVM control due to the FPGA’s high- bandwidth control loop implemented in hardware using parallel processing techniques.

Torque Ripple Comparison:

DTFC-SVM DSP Builder for Intel FPGAs Reference Design

The DSP Builder for Intel FPGAs for Intel FPGAs tool provides MathWorks’ Simulink design blocks and the ability to auto-generate HDL code. It also simplifies the design process by allowing engineers to directly implement into the FPGA the same model they used to simulate the system. In addition, it permits the designer to leverage a rich library of power electronics components when constructing the testbench or system simulation model.

DSP Builder for Intel FPGAs Design Flow

For more detailed information, download the FPGA-Based Control for Electric Vehicle and Hybrid Electric Vehicle Power Electronics white paper.

To help you kick start your development, Intel provides a design example for a hybrid EV DC-DC converter (variable voltage control or VVC) digital controller with predefined platform targeting a Intel® MAX® 10 FPGA. The architecture and theory are described in the white paper FPGA-Based Control for Electric Vehicle and Hybrid Electric Vehicle Power Electronics.

The design example uses the DSP Builder for Intel FPGAs Advanced Blockset to simulate and synthesize VHDL control. The VHDL is then targeted to a BeMicro MAX 10 Evaluation kit (available from Arrow Electronics).

Download Design Example from Intel Design Store ›

DSP Builder for Intel FPGAs Design Tool

The DSP Builder for Intel FPGAs tool provides Mathworks Simulink design blocks and the ability to auto-generate HDL code. It allows the same model used to simulate the system to be directly implemented into the FPGA. It also enables the designer to leverage a rich library of power electronics components when constructing the test bench or system simulation model.

For More Efficient Power Conversion

Faster switching allows you to reduce inductance and capacitance values to achieve equivalent voltage and current ripple. However, faster switching increases transistor switching losses and requires higher bandwidth, which are both challenges for an MCU-based system using IGBT.

FPGA-based high-frequency valuable voltage DC/DC converters (VVC) allow the use of smaller, lower-cost reactive components, and increasingly available high-speed switching silicon carbide (SiC) MOSFETs.

FPGAs offer:

• Cost effectiveness: FPGAs enable the use of smaller, lower-cost reactive components and high-speed switching silicon carbide (SiC) MOSFETs.
• Processing speed: Algorithms can be accelerated and parallelized as necessary in FPGA hardware.
• Scalability: Enhanced technologies, such as multi-level converters, can be implemented.
• Functional safety: Safety logic (a Clock checker, for instance) can be implemented to monitor MCU status as a fail-safe device.

A 5X increase in switching frequency reduces inductance and capacitance values for the same ripple current and voltage. These reductions reduce size and cost.

This increased bandwidth is a challenge for MCU-based solutions where multiple functions are implemented with one processor. FPGA control can easily provide the bandwidth, even if multiple control functions are implemented on one device.

Collaborating with the University of Pisa, Intel has released its first Battery Management System (BMS) reference design and application note. This reference design demonstrates the FPGA's complex parallel computing capability to estimate the State Of Charge (SOC) with a dual extended Kalman filter algorithm on a Intel® MAX® 10 FPGA in a system-in-loop model. It opens new possibilities to develop smarter BMSs to allow online SOC measurement methodology by off-loading complex algorithms to programmable hardware, freeing remaining CPU resources for other important tasks.

Download reference design and application note ›

Make Your Battery Management System Even Smarter

The battery is the most expensive component in an electric vehicle. Its cost has a direct impact on the value of the vehicle because driving mileage is determined primarily by battery capacity. The battery needs to be managed efficiently to make optimum use of the energy in its cells, and to prevent electrical damage to the cells, which shortens battery cycle life.

Low-cost microcontroller units (MCUs) are sufficient for basic control functions, but the increasing number of battery cell and functional safety requirements drives the need for better control methods and architecture to meet system costs and stringent safety criteria. FPGAs are ideal solution to these design challenges.

FPGAs offer:

• Performance improvement: Run more advanced algorithms faster and parallel to improve performance.
• System cost reduction: Integration of several components, monitor more modules/cells with multiple serial interfaces.
• Scalability: Support latest advanced interface protocol which is not on current MCUs.
• Safety: Implement hardware fail-safe logic.

Intel® MAX® 10 FPGAs enable you to implement unique features in your battery management system:

• System power control: Intel® MAX® 10 FPGAs offer a sleep mode by keeping state and wake-up within 1 msec.
• Dual boot image: Change operation mode per use case with a dual-boot image (i.e., driving vs. charging mode).

Two Architectural Approaches: Master or Companion

Intel supports two different architectural approaches to enhance your system while maximizing the benefit of programmable logic.

• Use the Intel® MAX® 10 FPGA as the system master with the embedded Nios® II soft processor core, which is a royalty-free, compact size real-time processor. You can visit here and download white paper to learn the benefits of using Intel® MAX® 10 FPGAs with the Nios II processor.
• Maximize performance and flexibility without major architectural changes. Intel® MAX® 10 FPGA can be a great companion solution to off-load complex algorithm processing from an existing CPU. For example, a Kalman filter can greatly improve the accuracy of the SOC in a BMS. You can implement it in a Intel® MAX® 10 FPGA as a hardware accelerator to improve system performance without changing the main processor.