spi_master_atlys_top Project Status
Project File: spi_ms_atlys_ct.xise Parser Errors:
Module Name: spi_master_atlys_top Implementation State: New
Target Device: xc6slx45-2csg324
  • Errors:
 
Product Version:ISE 13.1
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Current Errors [-]
No Errors Found
 
Current Warnings [-]
No Warnings Found
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/10/2011 - 22:47:40