spi_master_atlys_top Project Status (08/28/2011 - 23:35:14) | |||
Project File: | spi_ms_atlys.xise | Parser Errors: | No Errors |
Module Name: | spi_master_atlys_top | Implementation State: | Synthesized |
Target Device: | xc6slx45-2csg324 |
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No Errors |
Product Version: | ISE 13.1 |
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28 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 218 | 54576 | 0% | |
Number of Slice LUTs | 166 | 27288 | 0% | |
Number of fully used LUT-FF pairs | 112 | 272 | 41% | |
Number of bonded IOBs | 63 | 218 | 28% | |
Number of BUFG/BUFGCTRLs | 2 | 16 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Aug 28 23:35:13 2011 | 0 | 28 Warnings (0 new) | 24 Infos (0 new) | |
Translation Report | Out of Date | Sun Aug 28 23:23:42 2011 | 0 | 0 | 0 | |
Map Report | Out of Date | Sun Aug 28 23:24:01 2011 | 0 | 0 | 13 Infos (0 new) | |
Place and Route Report | Out of Date | Sun Aug 28 23:24:13 2011 | 0 | 1 Warning (0 new) | 4 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Sun Aug 28 23:24:19 2011 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Sun Aug 28 23:30:20 2011 | |
Post-Synthesis Simulation Model Report | Out of Date | Sun Aug 28 23:19:42 2011 | |
Post-Translate Simulation Model Report | Out of Date | Sun Aug 28 23:19:45 2011 | |
Post-Map Simulation Model Report | Out of Date | Sun Aug 28 23:20:15 2011 | |
Physical Synthesis Report | Out of Date | Sun Aug 28 23:24:01 2011 | |
Post-Place and Route Simulation Model Report | Out of Date | Sun Aug 28 23:24:26 2011 | |
WebTalk Report | Out of Date | Wed Aug 10 23:31:06 2011 |