Project Statistics |
PROPEXT_MapGlobalOptimization_spartan6=Area |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_MapLUTCombining_spartan6=Area |
PROP_ProjectDescription=Testbed for the spi master/slave cores for continuous transmission mode |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/testbench |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthExtractRAM=false |
PROP_SynthExtractROM=false |
PROP_SynthFsmEncode=Gray |
PROP_SynthOptEffort_spartan6=High |
PROP_SynthShiftRegExtract=false |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=C:/Xilinx/13.1/ISE_DS/ISE/data/default.xds |
PROP_UserConstraintEditorPreference=Constraints Editor |
PROP_VHDLSourceAnalysisStandard=VHDL-200X |
PROP_intProjectCreationTimestamp=2011-07-07T09:55:20 |
PROP_intWbtProjectID=2C5BE631B69F48AB8C2F24035AF7A13B |
PROP_intWbtProjectIteration=5 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.testbench |
PROP_selectedSimRootSourceNode_par=work.testbench |
PROP_selectedSimRootSourceNode_translate=work.testbench |
PROP_selectedSimSourceNode=Inst_spi_master_atlys_top |
PROP_xilxBitgStart_Clk_DriveDone=true |
PROP_xilxMapReportDetail=true |
PROP_xstLUTCombining_spartan6=Area |
PROP_AutoTop=false |
PROP_DevFamily=Spartan6 |
PROP_ISimSimulationRun_behav_tb=false |
PROP_ISimSimulationRun_translate_tb=false |
PROP_MapExtraEffort_spartan6=Normal |
PROP_xilxMapEnableMultiThreading=2 |
PROPEXT_xilxPARextraEffortLevel_spartan6=Normal |
PROP_DevDevice=xc6slx45 |
PROP_DevFamilyPMName=spartan6 |
PROP_ISimSimulationRunTime_behav_tb=30000 ns |
PROP_ISimSimulationRunTime_par_tb=12000 ns |
PROP_ISimSimulationRunTime_translate_tb=12 us |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_parEnableMultiThreading_spartan6=4 |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=5 |