q_sys

2014.05.27.18:44:28 Datasheet
Overview
  clk_0  q_sys

All Components
   i2c_cont_bridge_0 i2c_cont_bridge 1.0
   opencores_i2c_0 opencores_i2c 9.1
   System_max_ID_0 System_max_ID 1.0
Memory Map
vj_avalon_master_0 i2c_cont_bridge_0
 avalon_master  avalon_master
  i2c_cont_bridge_0
slv  0x00000000
  opencores_i2c_0
avalon_slave_0  0x00000000
  System_max_ID_0
slv  0x04000000

clk_0

clock_source v13.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

vj_avalon_master_0

vj_avalon_master v1.0
clk_0 clk   vj_avalon_master_0
  clock_sink
clk_reset  
  clock_sink_reset
avalon_master   i2c_cont_bridge_0
  slv
avalon_master   System_max_ID_0
  slv


Parameters

AUTO_CLOCK_SINK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

i2c_cont_bridge_0

i2c_cont_bridge v1.0
clk_0 clk_reset   i2c_cont_bridge_0
  reset
clk  
  clock
vj_avalon_master_0 avalon_master  
  slv
avalon_master   opencores_i2c_0
  avalon_slave_0


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

opencores_i2c_0

opencores_i2c v9.1
i2c_cont_bridge_0 avalon_master   opencores_i2c_0
  avalon_slave_0
clk_0 clk  
  clock
clk_reset  
  clock_reset


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

System_max_ID_0

System_max_ID v1.0
clk_0 clk_reset   System_max_ID_0
  reset
clk  
  clock
vj_avalon_master_0 avalon_master  
  slv


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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