|
Products
|
 |
 |
|
| Intel® 80200 Processor |
|
|
Features & Benefits | Product Highlights
 The Intel® 80200 processor is based on Intel XScale® microarchitecture and gives developers of a wide range of applications the ability to optimize the needs of their applications from ultra-low power to high-performance processing. The excellent core performance paves the way for extremely complex applications-especially applications that require processor intensive calculations.
The Intel 80200 processor can be used together with ASICs (Application Specific Integrated Circuits) or other companion chips to provide solutions customized for specific applications. For example, combining the Intel 80200 processor with an ASIC that includes a high-bandwidth PCI interface, memory controller and communication peripherals would provide a high-performance platform for advanced communication devices. Several companies have designed customized ASICs designed to interface with the external bus on the Intel 80200 processor. In addition, specifications for the external bus are available for use in designing custom companion chips for other applications.
The Intel 80200 processor, based on Intel XScale microarchitecture, is manufactured on Intel's 0.18-micron semiconductor process technology. This process technology enables the microprocessor core to operate over a wide range of speed and power, producing industry-leading mW/MIPS performance.
The Intel 80200 Processor - Greater I/O Performance Through Faster Cores
The Intel 80200 processor based on Intel XScale microarchitecture is available in four speed grades: 200MHz, 400 MHz, 600 MHz, and 733 MHz. The 80200T offers Extended Temperature versions of the same four speed grades, capable of being used in environments ranging from –40C to +85C. Offering multiple speed grades combined with Extended Temperature support |
|
|
|
|
enables developers to balance performance, power consumption, and cost, making the 80200 an excellent processor for a broad array of applications. Even at 733 MHz the Intel 80200 processor dissipates less than 1.3W! This is accomplished using the Intel® Superpipelined RISC Technology-the 7-stage integer, 8-stage memory superpipelined core achieves high speed with ultra-low power consumption.
High-performance applications can be further enhanced with use of the 32KB data and instruction caches. A 2KB mini-data cache is also included to help avoid "thrashing" of the data cache for frequently changing data streams. The combination of speed and larger caches allows users to implement complex applications and processor intensive calculations like audio encode/decode or video compression/decompression.
The Intel 80200 processor based on Intel XScale® microarchitecture is code compatible with the Intel® StrongARM* SA-110 processor. It is also compliant with ARM* v.5TE ISA. Users can maximize code density with the 16-bit Thumb* instruction set. The ARM v.5TE ISA executes either a 32-bit ARM instruction set or the Thumb instruction set.
Not Just Faster Cores - Many Other Features
The Intel XScale microarchitecture surrounds the core with instruction and data memory management units; instruction, data, and mini-data caches; write, fill, pend, and branch target buffers; power management, performance monitoring, debug, and JTAG units; coprocessor interface; and core memory bus.
Intel® Dynamic Voltage Management and frequency scaling on-the-fly allows designers to utilize the right blend of performance and power for their application.
Intel® Media Processing Technology provides a high level of integration between the execution core and advanced communication functions. The Intel 80200 processor includes a 40-bit Multiply Accumulate Unit, support for 16-bit SIMD, and DSP Extensions.
Intel® 80200 Processor
Based on Intel XScale® Microarchitecture Block Diagram
|
|
|
|
Features and Benefits
|
|
|
|
|
|
|
Features |
|
Benefits |
|
|
|
|
|
|
|
 |
Intel® Superpipelined Technology |
|
|
7-stage integer/8 memory superpipelined core achieves high speed and ultra-low power |
|
|
|
|
|
|
|
 |
Intel® Dynamic Voltage Management |
|
|
Dynamic voltage and frequency scaling on-the-fly allows applications to utilize the right blend of performance and power |
|
|
|
|
|
|
|
|
Intel® Media Processing Technology |
|
|
Multiply-accumulate coprocessor performs two simultaneous 16-bit SIMD multiplies with 40-bit accumulation for efficient media processing |
|
|
|
|
|
|
|
|
Power Management Unit |
|
|
Gives power savings via idle, sleep, and quick wake-up modes |
|
|
|
|
|
|
|
|
128-Entry Branch Target Buffer |
|
|
Keeps pipeline filled with statistically correct branch choices |
|
|
|
|
|
|
|
|
32KB Instruction Cache |
|
|
Keeps local copy of important instructions to enable high performance and low power |
|
|
|
|
|
|
|
|
32KB Data Cache |
|
|
Keeps local copy of important data to enable high performance and low power |
|
|
|
|
|
|
|
|
32-Entry Instruction Memory Management Unit |
|
|
Enables logical-to-physical address translation, access permissions, I-Cache attributes |
|
|
|
|
|
|
|
|
32-Entry Data Memory Management Unit |
|
|
Enables logical-to-physical address translation, access permissions, D-Cache attributes |
|
|
|
|
|
|
|
|
4-Entry Fill and Pend Buffers |
|
|
Promotes Core efficiency by allowing non-blocking and "hit-under-miss" operation with D-Caches |
|
|
|
|
|
|
|
|
Performance Monitoring Unit |
|
|
Furnishes two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc |
|
|
|
|
|
|
|
|
Debug Unit |
|
|
Uses Hardware Breakpoints and 256-entry Trace History Buffer (for flow change messages) to debug programs |
|
|
|
|
|
|
|
|
32-Bit Coprocessor Interface |
|
|
Provides high performance interface between core and coprocessors |
|
|
|
|
|
|
|
|
64-Bit Core Memory Bus with simultaneous 32-bit input path and 32-bit output path |
|
|
Gives up to 4.8GB/sec. @ 600 MHz bandwidth for internal accesses |
|
|
|
|
|
|
|
|
8-Entry Write Buffer |
|
|
Allows the Core to continue execution while data is written to memory |
|
|
|
|
|
|
|
|
|
|
|
|
|
Intel® 80200 Processor
Based on Intel XScale® Microarchitecture Performance Characteristics
|
|
|
|
Product Highlights
|
|
|
|
|
|
|
32-bit high-performance CPU (400, 600, 733 MHz) based on Intel XScale® Microarchitecture |
|
|
|
|
|
|
|
|
ARM* v.5TE compliant |
|
|
|
|
|
Intel® Superpipelined RISC technology 7-stage integer/8-stage memory superpipelined core—high core speeds with low power |
|
|
|
|
|
32KB data and instruction caches |
|
|
|
|
|
2KB mini data cache for accelerated streaming |
|
|
|
|
|
Power Management Unit |
|
|
|
|
|
128-entry Branch Target Buffer |
|
|
|
|
|
32-entry Instruction, 32-entry Data Memory Management Units |
|
|
|
|
|
Performance Monitoring Unit |
|
|
|
|
|
32-bit Coprocessor Interface |
|
|
|
|
|
64-bit Core Memory Bus with ECC |
|
|
|
|
|
|
|
|
|
